Hytec Electronics Ltd 8424TR/UTM/G/11/2.0
Page 11
5.1 Control & Status Register (CSR)
Control
Write Address: 0hex
D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00
ARM
EX ST XC ET EE FE HE 1M DA EII MII x CC F HF
Status
Read Address: 0hex
D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00
ARM
EX ST XC ET EE FE HE 1M DA EII MII MIS
CC F HF
ARM Arm the ADCs:-
If EX=’0’ and MIS=’0’ Continuous mode, here data is acquiring to the memory and registers
until the unit is disarmed. Memory will continuously wrap around.
If EX=’0’ and MIS =’1’ Gate Mode data is acquiring to memory for the period when the IP
Strobe* line is High (memory will wrap when reaches the end). Register updated continuously.
If EX=’1’ and MIS =’x’ Trigger mode waits for internal or external trigger.
EX Enable trigger. If not set continuously sample at the clock rate. If set allows external trigger or
software trigger
ST Software trigger. Triggers a programmed number of samples. ST is cleared on completion.
XC Enable the external clock. If 0 the internal clock is used for the sample rate. If set true the external
clock is used for the sample clock without frequency division.
ET A logic ‘0’ disable hardware memory inhibit input or Gate Mode. When logic ‘1’ enable
hardware memory inhibit or Gate in Gate Mode from IP Strobe* line. (on Hytec 800x IP carrier
card, this signal is driven from the front panel INHIBIT lemo).
EE Enables interrupt at end of sampling sequence.
FE Enables interrupt when the upper conversion memory has been filled. (Memory Full).
HE Enables interrupt when the lower conversion memory has been filled. (Memory Half Full).
1M Enables 1Mb memory (64K samples/channel) when logic 1 and 2Mb (128K samples/channel)
when logic 0.
DA Set to 1 allows the unit to disarm on completion of memory acquisition. Set which event this
occurs on by setting EE, FE or HE. In Continues mode EE has no function and does not clear
ARM. FE and HE will clear the ARM bit even when IP Strobe* line is High.
EII This enables an interrupt to be generated when ever the memory inhibit bit (MIS) is set.
MII
(Write) When set to logic ‘1’ hardware memory inhibit interrupt is cleared but not disabled.
(Read) Shows that an interrupt has been generated from hardware memory inhibit.
MIS (Read Only) this bit indicates that the hardware memory inhibited/gate on the IP Strobe* line is
asserted when at logic ‘1’ (driven from the front panel INHIBIT lemo on Hytec 800x IP carriers).
CC Conversions complete. Status bit set when the number of programmed samples has been
completed. Generates IRQ0* if set and EE is set to a logic 1. Clear by writing ‘0’ to this bit this
removes the interrupt and allows the unit to be triggered again (when not set in continues mode).
In continues mode this bit is set after the first programmed number of samples has been
completed. Again this bit can be cleared by writing ‘0’ and will again set its self after the next
programmed number of samples has been completed.
F Full status. Set when the upper conversion memory has been filled. Generates IRQ0* if set and
FE is set to a logic 1.
HF Half full status. Set when the lower conversion memory has been filled. Generates IRQ0* if set
and HE is set to a logic 1.
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