Enable-IT 8424 Manual do Utilizador descarregar pdf (Página 7)

Hytec Electronics Ltd 8424TR/UTM/G/7/2.0

Page 7

3. Operating Modes

3.1 Register mode

This mode is enabled by setting ARM = ‘1’ (bit 15 of the CSR) and EX=’0’ (bit 14 of the CSR).

As soon as the ARM bit is set (no trigger required) the ADCs sample at the sample rate which is derived

either from the internal clock whose rate is set by the Internal Sample Rate register or by the external

sample clock supplied by the user via the rear transition card see .

The ADC data registers are updated at the conversion rate. These registers can be read in any order at

any time.

The memory is also updated at the sample rate and is continuously updated rapping round on reaching the

end of the memory until the ARM bit is cleared.

There are four ADC buffer registers (addresses 10hex – 16hex) which store the last sampled conversions

and may be read at any time. The channel order is channel 1 at address 10hex to channel 4 at address

16hex.

D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00

Data

Data format 000Fh = –10v, 8000h = 0V and FFF1h = +10V.

Data format 000Fh = –5v, 8000h = 0V and FFF1h = +5V.

3.2 Triggered sampling

This mode is enabled by setting ARM = ‘1’ (bit 15 of the CSR) and EX=’1’ (bit 14 of the CSR). Then

when a software or hardware trigger is detected conversions are stored in the RAM memory at the sample

rate set.

The sample rate is derived either from the internal clock whose rate is set by the Internal Clock Rate

The value written to the memory pointer register gives the starting point in memory that the conversions

are stored to.

The point at which conversions are stopped is set by the Number of Counts register.

The address the unit stops at is given by the Memory Conversion pointer register.

This mode also updates the ADC Data registers at the conversion rate. These registers can be read in any

order at any time.

The Hardware trigger can be set by a bit in the extended CSR to trigger on the rising edge or falling edge

or both. The unit defaults to Rising edge.

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