Hytec Electronics Ltd 8424TR/UTM/G/15/2.0
Page 15
5.8 Digital Potentiometer Data Register
Read/write Address: Byte 20hex (Word 10hex)
This is used for calibration only during production test on the units.
D15
D14
D13
D12
D11
D10
D09
D08
D07
D06
D05
D04
D03
D02
D01
D00
EN PD CWR
X X X P9 P8 P7 P6 P5 P4 P3 P2 P1 P0
The ‘EN’ (bit 15) when set as a ‘1’ will cause the current value of the register to be down loaded to the
10bit digital pot. On completion of the write the EN bit is cleared. The rest of the contents of the register
remain unaltered.
PD bit when set to ‘1’ loads the pre loaded digital pot range data held in FPGA flash to registers in the
FPGA. This action is automatically done at boot up.
CWR bit copies wiper register value of the digital pot to the non-volatile register in digital pot. This can
be used to fine tune the gain.
The user can use this register to tweak the gain error of the unit if required. This maybe also be used to
compensate for ambient temperature or when external clocking is used.
5.9 Digital Potentiometer Calibration Registers
Read Address: Byte 22hex – 28hex (Word 11hex – 14hex)
D15
D14
D13
D12
D11
D10
D09
D08
D07
D06
D05
D04
D03
D02
D01
D00
X X X X X X P9 P8 P7 P6 P5 P4 P3 P2 P1 P0
These four registers hold the digital pot calibration factor for each of the ADCs voltage ranges. The
values are loaded at power up from the FPGA flash or when ‘PD’ (bit 14) of the digital pot register is set
to ‘1’ this is cleared at the finish.
When the range is changed the data held in the associated register is loaded to the digital potentiometer.
The calibration values held in the FPGA flash are programmed in during production test.
The digital pot can still be changed using the Digital Potentiometer Register above but the digital pot will
reload its self from the calibration registers on power up and on a range change.
6. ADC OPERATION
6.1 Memory Update Inhibit and Interrupt
The updating of the conversion memory can be stopped by controlling the external IP Strobe* line (on
the Hytec 8002 IP carrier card, this signal is driven from the front panel INHIBIT lemo).
When the STROBE line is taken low and the enable hardware memory inhibit bit (ET) is set in CSR the
updating of the conversion memory is stopped. This is indicated by the MIS bit in the CSR going high.
On memory update inhibit an interrupt can be generated if the Enable Memory Inhibit Interrupt enable bit
(EII) is set in the CSR. The Memory Inhibit Interrupt (MII) bit of the CSR flags an interrupt. This is
cleared by either clearing the EII in the CSR or by writing a ‘1’ to MII bit in the CSR which clears the
Memory Inhibit Interrupt without the need to clear the EII in the CSR.
The IP Strobe* line needs to be taken high then low after interrupt cleared to generate a new interrupt.
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