Enable-IT 8424 Manual do Utilizador descarregar pdf (Página 14)

Hytec Electronics Ltd 8424TR/UTM/G/14/2.0

Page 14

5.6 Number Of Conversions

Read/write Address: Chex - Ehex

The number of conversions register allows the number of conversions per trigger to be programmed.

If a number of triggers occur and the memory buffer size of 256K (128 in 1M mode) of conversions per

channel is exceeded the conversions will wrap around from the top of the memory to the bottom of the

memory if the continuous bit is set in the CSR Ext register.

Lower word Chex

D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00

N15 N14 N13 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 N0

Upper word Ehex

D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00

x x x x x x x x x x x x x N18 N17 N16

The following should be loaded in to the NOC to output whole or half the memory for the following

memory sizes as set by 1M bit 7 in CSR.

NOC Values

Memory Size

Half Full Full

2Mb (1M=0)

0x20000

(128K samples)

0X40000

(256K samples)

1Mb (1M=1)

0x10000

(64K samples)

0x20000

(128K samples)

When 1Mb is set it only changes when the Full and Half Full flags and interrupts occur as shown in the

above table. The user must ensure that the correct NOC value is entered as the setting of the 1Mb in the

CSR does not effect the NOC operation.

5.7 ADC Registers

Read only Address: 10hex – 16hex

The four ADC buffer registers store the last sample conversions and may be read at any time.

+/-10V range Data format 000Fh = –10v, 8000h = 0V and FFF1h = +10V.

+/-5V range Data format 000Fh = –5v, 8000h = 0V and FFF1h = +5V.

D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00

C15

C14

C13

C12

C11

C10

C9 C8 C7 C6 C5 C4 C3 C2 C1 C0

1 2 ... 9 10 11 12 13 14 15 16 17 18 19 ... 30 31

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